This invention relates to an integrated circuit structure comprising a capacitor element, and corresponding manufacturing methods. Specifically, this invention relates particularly, but not exclusively, to a circuit structure which is easier to integrate than prior ones comprising CMOS or MOS devices and capacitor elements, such as ferroelectric devices.
As is well known, ferroelectric devices, such as ferroelectric non-volatile memories, are acquiring growing importance in the field of integrate circuits, on account of their low consumption and high operational and switching speed compared to conventional non-volatile memories. In particular, special attention is being devoted to making such ferroelectric devices in combination with MOS devices integrated on a semiconductor substrate.
According to the prior art, these ferroelectric devices are formed after completing a CMOS structure to which they are subsequently connected, prior to forming the final metallization layers.
A known embodiment of these ferroelectric devices provides, after MOS devices, such as MOS transistors, etc., are formed in a semiconductor substrate, for an upper insulating layer to be formed over the entire chip surface. The ferroelectric device, e.g., a ferroelectric memory, is then formed which has a metal bottom electrode laid onto the upper insulating layer. A layer of a ferroelectric material covers the bottom electrode, and a metal upper electrode is laid onto the ferroelectric layer.
After isolating the ferroelectric device by means of another insulating layer, the electric connection between the upper electrode and conductive terminals of the MOS device is established.
According to the prior art, the ferroelectric device is formed on top of the insulating layer which covers MOS devices. This insulating layer may be a layer of doped oxide such as BPSG (Boron-Phosphorus-Silicon Glass).
While being advantageous in several ways, this solution has certain drawbacks tied to the thickness of the BPSG layer. In order to provide satisfactory planarization characteristics for the device surface, this thickness must be sufficiently large. It is also necessary to carry out thermal reflow cycles which may affect the characteristics of the device active regions. Forming openings for the device contacts in a fairly thick oxide layer such as this often poses objective difficulties from the fairly deep digging that must be performed therein.
Embodiments of this invention provide a circuit structure comprising both electronic devices formed with CMOS technology and capacitor elements, which have such structural and functional features to enable contact areas to be provided with a low aspect ratio (ratio of the contact depth to width), and a better integrated and more compact overall circuit structure, thereby overcoming the limitations and/or drawbacks of prior art circuit structures.
One of the concepts behind embodiments of this invention is to provide a circuit structure which comprises MOS devices integrated on a semiconductor substrate and covered with an unreflowed oxide layer, such as TEOS, and comprises capacitor elements formed above this oxide layer. The use of a TEOS layer for covering the MOS devices in the circuit structure of certain embodiments allows the thickness of the layer to be reduced wherein the openings are formed for the contacts used for connecting the MOS devices to the capacitor elements.
The features and advantages of a device according to the invention will be apparent from the following description of an embodiment thereof, given by way of nonlimitative example with reference to the accompanying drawings.